Structure that holds the features of the CPU. More...
Public Types | |
enum | eCPU { kCPUIntel , kCPUAMD , kCPUCentaur , kCPUCyrix , kCPUTransmeta , kCPUNationalSemiconductor , kCPUNexgen , kCPURise , kCPUSIS , kCPUUMC , kCPUVIA , kCPUVortex , kCPUShanghai , kCPUHygon , kCPURDC , kCPUElbrus2000 , kCPUMiSTer486 , kCPUKVM , kCPUMicrosoftVirtualPC , kCPUParallels , kCPUVMWare , kCPUXen , kCPURosetta2 , kCPUUnknown } |
Intel CPU enumeration. More... | |
Public Member Functions | |
uint_t | has_RTSC (void) const noexcept |
Returns non-zero if the RTSC instruction is available. | |
uint_t | has_CMOV (void) const noexcept |
Returns non-zero if the CMOV instructions are available. | |
uint_t | has_MMX (void) const noexcept |
Returns non-zero if the MMX instructions are available. | |
uint_t | has_SSE (void) const noexcept |
Returns non-zero if SSE instructions are available. | |
uint_t | has_SSE2 (void) const noexcept |
Returns non-zero if SSE2 instructions are available. | |
uint_t | has_SSE3 (void) const noexcept |
Returns non-zero if SSE3 instructions are available. | |
uint_t | has_SSSE3 (void) const noexcept |
Returns non-zero if SSSE3 instructions are available. | |
uint_t | has_SSE4a (void) const noexcept |
Returns non-zero if SSE4a instructions are available. | |
uint_t | has_SSE41 (void) const noexcept |
Returns non-zero if SSE4.1 instructions are available. | |
uint_t | has_SSE42 (void) const noexcept |
Returns non-zero if SSE4.2 instructions are available. | |
uint_t | has_MOVBE (void) const noexcept |
Returns non-zero if the MOVBE instruction is available. | |
uint_t | has_AES (void) const noexcept |
Returns non-zero if AES instructions are available. | |
uint_t | has_AVX (void) const noexcept |
Returns non-zero if AVX instructions are available. | |
uint_t | has_AVX2 (void) const noexcept |
Returns non-zero if AVX2 instructions are available. | |
uint_t | has_CMPXCHG16B (void) const noexcept |
Returns non-zero if the CMPXCHG16B instruction is available. | |
uint_t | has_F16C (void) const noexcept |
Returns non-zero if the F16C data type is supported. | |
uint_t | has_FMA3 (void) const noexcept |
Returns non-zero if FMA3 instructions are available. | |
uint_t | has_FMA4 (void) const noexcept |
Returns non-zero if FMA4 instructions are available. | |
uint_t | has_LAHFSAHF (void) const noexcept |
Returns non-zero if LAHF and SAHF instructions support long mode. | |
uint_t | has_PrefetchW (void) const noexcept |
Returns non-zero if PrefetchW instructions are available. | |
uint_t | has_3DNOW (void) const noexcept |
Returns non-zero if AMD 3DNow! instructions are available. | |
uint_t | has_extended3DNOW (void) const noexcept |
Returns non-zero if extended AMD 3DNow! instructions are available. | |
Public Attributes | |
uint64_t | m_uXGETBV |
Result from XGETBV(0) | |
uint32_t | m_uHighestCPUID |
Highest allowed CPUID input (0 if CPUID is not present) | |
uint32_t | m_uHighestCPUIDExtended |
Highest allowed extended CPUID (0x80000000 and up or zero) | |
uint32_t | m_uHighestCPUIDHyperVisor |
Highest allowed hypervisor CPUID (0x40000000 and up or zero) | |
uint32_t | m_uModel |
Model information CPUID(1) -> EAX. | |
uint32_t | m_uBrand |
Brand information CPUID(1) -> EBX. | |
uint32_t | m_uCPUID1ECX |
Extended feature information CPUID(1) -> ECX. | |
uint32_t | m_uCPUID1EDX |
Feature information CPUID(1) -> EDX. | |
uint32_t | m_uCPUID80000001ECX |
Extended feature bits CPUID(0x80000001) -> ECX. | |
uint32_t | m_uCPUID80000001EDX |
Extended processor info CPUID(0x80000001) -> EDX. | |
uint32_t | m_uCPUID7EBX |
Feature bits CPUID(7) -> EBX. | |
uint32_t | m_uCPUID7ECX |
Feature bits CPUID(7) -> ECX. | |
uint32_t | m_uCPUID7EDX |
Feature bits CPUID(7) -> EDX. | |
uint32_t | m_uMXCSR |
MXCSR. | |
eCPU | m_uCPUType |
Enumeration of the manufacturer of the CPU. | |
char | m_CPUName [16] |
12 character brand name of the CPU (Null terminated) | |
char | m_BrandName [52] |
48 character full name of the CPU (Null terminated) | |
char | m_HypervisorName [16] |
12 character full name of the hypervisor (Null terminated) | |
char | m_HypervisorSignature [8] |
4 character hypervisor signature (Null terminated) | |
Structure that holds the features of the CPU.
On x86 and x64 CPUs, this structure will be filled by the use of the instruction CPUID on Intel architecture CPUs.
Intel CPU enumeration.
Returned by CPUID(CPUID_t*) to list the manufacturer of the Intel type CPU current executing the application's code.
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inlinenoexcept |
Returns non-zero if AMD 3DNow! instructions are available.
https://en.wikipedia.org/wiki/3DNow!
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inlinenoexcept |
Returns non-zero if AES instructions are available.
https://en.wikipedia.org/wiki/AES_instruction_set
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inlinenoexcept |
Returns non-zero if AVX instructions are available.
https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
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inlinenoexcept |
Returns non-zero if AVX2 instructions are available.
https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
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inlinenoexcept |
Returns non-zero if the CMOV instructions are available.
https://en.wikipedia.org/wiki/FCMOV
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inlinenoexcept |
Returns non-zero if the CMPXCHG16B instruction is available.
http://www.felixcloutier.com/x86/CMPXCHG8B:CMPXCHG16B.html
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inlinenoexcept |
Returns non-zero if extended AMD 3DNow! instructions are available.
https://en.wikipedia.org/wiki/3DNow!#3DNow_extensions
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inlinenoexcept |
Returns non-zero if the F16C data type is supported.
https://en.wikipedia.org/wiki/F16C
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inlinenoexcept |
Returns non-zero if FMA3 instructions are available.
https://en.wikipedia.org/wiki/FMA_instruction_set
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inlinenoexcept |
Returns non-zero if FMA4 instructions are available.
https://en.wikipedia.org/wiki/FMA_instruction_set#FMA4_instruction_set
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inlinenoexcept |
Returns non-zero if LAHF and SAHF instructions support long mode.
http://www.tptp.cc/mirrors/siyobik.info/instruction/LAHF.html
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inlinenoexcept |
Returns non-zero if the MMX instructions are available.
https://en.wikipedia.org/wiki/MMX_(instruction_set)
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inlinenoexcept |
Returns non-zero if the MOVBE instruction is available.
https://www.tptp.cc/mirrors/siyobik.info/instruction/MOVBE.html
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inlinenoexcept |
Returns non-zero if PrefetchW instructions are available.
http://www.felixcloutier.com/x86/PREFETCHW.html
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inlinenoexcept |
Returns non-zero if the RTSC instruction is available.
https://en.wikipedia.org/wiki/Time_Stamp_Counter
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inlinenoexcept |
Returns non-zero if SSE instructions are available.
https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions
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inlinenoexcept |
Returns non-zero if SSE2 instructions are available.
https://en.wikipedia.org/wiki/SSE2
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inlinenoexcept |
Returns non-zero if SSE3 instructions are available.
https://en.wikipedia.org/wiki/SSE3
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inlinenoexcept |
Returns non-zero if SSE4.1 instructions are available.
https://en.wikipedia.org/wiki/SSE4#SSE4.1
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inlinenoexcept |
Returns non-zero if SSE4.2 instructions are available.
https://en.wikipedia.org/wiki/SSE4#SSE4.2
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inlinenoexcept |
Returns non-zero if SSE4a instructions are available.
https://en.wikipedia.org/wiki/SSE4#SSE4a
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inlinenoexcept |
Returns non-zero if SSSE3 instructions are available.
https://en.wikipedia.org/wiki/SSSE3
char Burger::CPUID_t::m_BrandName[52] |
48 character full name of the CPU (Null terminated)
char Burger::CPUID_t::m_CPUName[16] |
12 character brand name of the CPU (Null terminated)
char Burger::CPUID_t::m_HypervisorName[16] |
12 character full name of the hypervisor (Null terminated)
char Burger::CPUID_t::m_HypervisorSignature[8] |
4 character hypervisor signature (Null terminated)
uint32_t Burger::CPUID_t::m_uBrand |
Brand information CPUID(1) -> EBX.
uint32_t Burger::CPUID_t::m_uCPUID1ECX |
Extended feature information CPUID(1) -> ECX.
uint32_t Burger::CPUID_t::m_uCPUID1EDX |
Feature information CPUID(1) -> EDX.
uint32_t Burger::CPUID_t::m_uCPUID7EBX |
Feature bits CPUID(7) -> EBX.
uint32_t Burger::CPUID_t::m_uCPUID7ECX |
Feature bits CPUID(7) -> ECX.
uint32_t Burger::CPUID_t::m_uCPUID7EDX |
Feature bits CPUID(7) -> EDX.
uint32_t Burger::CPUID_t::m_uCPUID80000001ECX |
Extended feature bits CPUID(0x80000001) -> ECX.
uint32_t Burger::CPUID_t::m_uCPUID80000001EDX |
Extended processor info CPUID(0x80000001) -> EDX.
eCPU Burger::CPUID_t::m_uCPUType |
Enumeration of the manufacturer of the CPU.
uint32_t Burger::CPUID_t::m_uHighestCPUID |
Highest allowed CPUID input (0 if CPUID is not present)
uint32_t Burger::CPUID_t::m_uHighestCPUIDExtended |
Highest allowed extended CPUID (0x80000000 and up or zero)
uint32_t Burger::CPUID_t::m_uHighestCPUIDHyperVisor |
Highest allowed hypervisor CPUID (0x40000000 and up or zero)
uint32_t Burger::CPUID_t::m_uModel |
Model information CPUID(1) -> EAX.
uint32_t Burger::CPUID_t::m_uMXCSR |
MXCSR.
uint64_t Burger::CPUID_t::m_uXGETBV |
Result from XGETBV(0)